Hard disk adapter

Adapter Registers

The following registers are implemented within the M3SE FPGA:

	Port 0xC0 (RO): Adapter Status
		 Bit  7  - Drive 0 hardware write protect (always 0)
		 Bit  6  - Drive 1 hardware write protect (always 0)
		 Bit  5  - Drive 2 hardware write protect (always 0)
		 Bit  4  - Drive 3 hardware write protect (always 0)
		 Bit  0  - IDE interrupt status
	Port 0xC1 (R/W): Adapter Control
		Bits 7:5 - No function  
		 Bit  4  - Software reset (not implemented)
		 Bit  3  - Device enable (not implemented)
		Bits 2:1 - No function
		 Bit  0  - IDE interrupt enable
	Port 0xC2 (RO): Adapter Presence Detect
		Bits 7:0 - Constant 0x01
	Port 0xC3 (R/W): IDE Data MSB
		Bits 7:0 - IDE data most significant byte
	Port 0xC4 (R/W): Hard Disk Image Select
		Bits 6:1 - Cylinder set select (IDE cylinder number MSB bits 7:2)
		 Bit  0  - Head set select (IDE head number bit 3)

The "head set select" bit in port 0xC4 resets to 0 if DIP switch 1 is in the OFF position, and 1 if the switch is in the ON position, providing a means of selecting which image (0 or 1) is booted at system powerup or reset.

IDE Device Registers

The following registers are, except as noted, implemented within the IDE devices--usually CF cards, in the case of M3SE:

	Port 0xC6 (R/W): IDE Alternate Status (Read), Device Control (Write)
	Port 0xC7 (RO): IDE Drive Address
	Port 0xC8 (R/W): IDE Data LSB
		Bits 7:0 - IDE data least significant byte
	Port 0xC9 (R/W): IDE Error Status (read), Features (write)
	Port 0xCA (R/W): IDE Sector Count
		Bits 7:0 - IDE sector count
	Port 0xCB (R/W): IDE Sector Number - 1
		Bits 7:0 - IDE sector number - 1

When writing to port 0xCB, the M3SE adds one to the value sent to the IDE device. When reading port 0xCB, M3SE subtracts one from the value presented to the TRS-80. This provides maximum compatibility with the RSHARD MFM hard disk drivers from the RSHARD1 package, since MFM sector numbers start at 0 but IDE sector numbers start with 1.

	Port 0xCC (R/W): IDE Cylinder Number LSB
		Bits 7:0 = Cylinder number least significant byte
	Port 0xCD (R/W): IDE Cylinder Number MSB
		Bits 7:2 - See below
		Bits 1:0 - Cylinder number most significant byte bits 1:0

When writing to port 0xCD, bits 7:2 of the value sent to the IDE device are taken from port 0xC4 bits 6:1. This allows LDOS to access multiple hard disk images with IDE cylinder numbers beyond 1023. When reading port 0xCD, the cylinder number MSB returned by the selected IDE device is passed intact to the TRS-80.

	Port 0xCE (R/W): IDE Drive/Head
		Bits 7:5 - Should read constant 0x5 (IDE ECC/sector size parameters)
		 Bit  4  - Select secondary (slave) drive
		 Bit  3  - See below
		Bits 2:0 - Head number bits 2:0

When writing to port 0xCE, bit 3 of the value sent to the IDE device--bit 3 of the head number--is taken from port 0xC4 bit 0. This allows LDOS to access multiple hard disk images with head numbers in the 8-15 range. When reading port 0xCE, the IDE drive/head value returned by the selected IDE device is passed intact to the TRS-80.

	Port 0xCF (R/W): IDE Status (Read), Command (Write)

IDE Interrupt

The IDE interrupt signal is routed to the TRS-80, allowing interrupt-driven hard drive access. Before enabling the interrupt, you must have an interrupt service routine in place. The service routine must clear the interrupt source (normally by reading the IDE Status register at port 0xCF) before returning.

Alternatively, IDE interrupt status can be polled at port 0xC0 bit 0.

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